In a multilayer printed circuit board (PCB), there are occasions that signals have to switch signaling planes in the PCB. FIGS. 1A and 1B illustrate such signal plane switching. As best shown in the cross sectional view of FIG. 1B, a signal trace 18t originally proceeding on the top of a PCB 15 meets with a via 18 appearing through the PCB 15 and down to another signal trace 18b on the bottom of the PCB 15. Thus, by use of the via 18, the signal trace is allowed to change planes in the printed circuit board, which can facilitate signal routing.
Also present in the PCB 15 are power (i.e., Vdd) and ground planes, respectively numbered as 12, 14, and referred to collectively as “power planes.” These power planes 12, 14 allow power and ground to be routed to the various devices mounted on the board (not shown). (Although shown with the power plane 14 on top of the ground plane 12, these planes can be reversed). When routing a signal through these power planes, it is necessary to space the via 18 from both planes 12, 14, what is referred to as an antipad diameter 12h, 14h. The vias themselves at the level of the signal planes have pads to facilitate routing of the signals 18t, 18b to the via, which have a pad diameter (18p) larger than the diameter of the via 18 itself (d). Typical values for the diameter of the via (d), the pad diameter (18p) and the antipad diameter (12h, 14h) are 16, 20, and 24 mils respectively. It should be understood that an actual PCB 15 might have several different signal and power planes, as well as more than two signal planes, although not shown for clarity.
When a signal trace such as 18t, 18b switches signal planes, the signal return current—a transient—will generate electromagnetic (EM) waves that propagate in the cavity 17 formed between the power and ground planes 12, 14. Such EM waves will cause electrical disturbance on the signal being switched, as well as other signals traces. Such disturbances are especially felt in other near-by signals traces that are also switching signal planes, such as signal traces 16t, 16b (FIG. 1A) due to coupling between the vias (i.e., 18 and 16). Moreover, such EM disturbances are significantly enhanced around the resonant frequencies of the power/ground cavity 17, which in turn are determined by the physical dimensions of the power planes 12, 14. Via-to-via coupling induced by signal plane switching can cause significant cross-talk, and can be particularly problematic for high frequency switching applications.
FIGS. 2 and 3, representing computer simulations on the structure of FIG. 1A, illustrate these problems. In these simulations, one of the signal lines (say, signal 16) is an “aggressor” through which a simulated signal is passed, and the other signal line (signal 18) is the “victim” whose perturbation is monitored. The simulations were run in HFSS™, which is a full-wave three-dimensional EM solver available from Ansoft Corporation of Pittsburgh, Pa. The simulations were run assuming a 2.0-by-0.4 inch PCB 15, a spacing of 100 mils between the two vias 16, 18, a height of 54 mils between the power planes 12, 14 defining the cavity 17, and use of an FR4 dielectric for the PCB 16 (with a dielectric constant of 4.2). Traces 16t, 16b, 18t, and 18b were assumed to be microstrip lines with a characteristic impedance of 40 ohms. Via diameters, via pad diameters, and antipad diameters were assumed to have the values mentioned previously.
FIG. 2 shows the transmission coefficient of the aggressor signal, and significant signal loss is observed around certain resonant frequencies. The measured parameter is a scattering parameter (S-parameter), which is a standard metric for signal integrity and which is indicative of the magnitude of the EM disturbance caused by signal plane switching. FIG. 3 shows the coupling coefficient between the aggressor and victim signals. As can be seen, the coupling coefficient stands close to −10 db around all resonance frequencies, indicating significant cross-talk between the aggressor and the victim.
The prior art has sought to remedy these problems in a number of different ways. First, as disclosed in Houfei Chen et al., “Coupling of Large Numbers of Vias in Electronic Packaging Structures and Differential Signaling,” IEEE MTT-S International Microwave Symposium, Seattle, Wash., Jun. 2-7 (2002), it was taught to surround vias of interest in a PCB with shielding vias. In U.S. Pat. No. 6,789,241, it was taught to place decoupling capacitors between the power and ground planes on a PCB at different locations. In Thomas Neu, “Designing Controlled Impedance Vias,” at 67-72, EDN (Oct. 2, 2003), it was taught to minimize the impedance discontinuity caused by the via structure by adding four companion vias, all connected to ground planes. All of these references cited in this paragraph are hereby incorporated by reference.
However, these prior approaches suffer from drawbacks, as will be discussed in further detail later. In any event, the art would be benefited from strategies designed to minimize problems associated with signals switching signal planes in a printed circuit board. This disclosure provides such a solution in the form of an improved, shielded via structure.